1. Field of the Invention
The invention relates to distributed processing systems. More particularly, the invention relates to distributed processing systems which incorporate a plurality of processing zones (referred to herein as "cells"), each cell processing information in response to a type of event, and each cell communicating with other cells according to an event-reaction protocol as well as according to other protocols such as streaming, broadcast, etc. Cells exhibit a symmetrical and reciprocal relationship, with cells sometimes being a controller of other cells and sometimes being controlled by other cells. The system is self-configuring, self-repairing, and operates in real time.
2. State of the Art
So-called "distributed processing" or "parallel processing" systems generally employ multiple processors in order to speed the execution of a single program or to enable the simultaneous execution of several programs. Distributed processing embraces almost any computing system where processing of data occurs in more than one CPU. A simple example of distributed computing is printing from a PC to an image processing printer which has its own processor. The task of printing is distributed between the processor in the PC and the processor in the printer. In almost every case of "distributed processing" or "parallel processing" the distribution of tasks is controlled by a central controller processor. Thus, while processing may be distributed, "intelligence" is not distributed. The "intelligence" to decide how processes will be distributed remains centralized and limited.
U.S. Pat. No. 5,095,522 to Fujita et al. discloses an object-oriented parallel processing system which utilizes "concept objects" and "instance objects". The system utilizes a host processor and a plurality of general purpose processors which are programmed by the host processor. The host user must program (generate concept and instance objects) for each processor before parallel processing can begin. Fujita et al. considers this aspect of their system to be a feature which allows dynamic changes in the functionality of each of the processors. However, this aspect of their system greatly complicates the host processor software.
Similarly, U.S. Pat. No. 5,165,018 to Simor describes a system in which "nodes" are provided with generic configuration rules and are configured at runtime via resource definition messages from the control node. Simor considers this aspect of his system to be an advantage which, among other things, "isolates the hardware from the software" and "allows programs to be written as if they were going to be executed on a single processor." In addition, Simor's system permits programs to be "distributed across multiple processors without having been explicitly designed for that purpose."
Both Fujita et al. and Simor utilize general purpose processors and attempt to isolate the hardware from the software, freeing the programmer to write code as if it were being executed on a single processor. However, as mentioned above, writing multithreaded software for a single processor is very complex. Neither Fujita et al. nor Simor offer any solution for this complexity.
3. Related Inventions
Co-owned prior application Ser. No. 08/525,948, now U.S. Pat. No. 5,708,838, approaches the problem of distributed processing in a manner which is completely different from that of either Fujita et al. or Simor. The system disclosed in the '948 application utilizes processors which have been pre-programmed with functionality for a specific purpose and thereby integrates hardware with software. The developer chooses specific hardware (object oriented processors) in a manner similar to choosing specific software objects. This approach requires that the developer be very aware of the hardware used in the system, but frees the developer from writing much of the code used to implement the system. Accordingly, the developer need only write a minimal amount of relatively high level code to link the pre-programmed object oriented processors which contain statically stored code for performing specific tasks and to parametrically program the processors where desired. This approach is based on the belief that writing and de-bugging code is more time consuming and more expensive than linking together processors which contain pre-written, pre-tested, bug-free code. This approach enables rapid system development, relieves the host processor of many scheduling tasks, simplifies de-bugging, enables cross-platform support, and allows software emulation of hardware devices, as well as providing other advantages.
Co-owned prior application Ser. No. 08/683,625, now U.S. Pat. No. 6,072,944, discloses a distributed processing system where one or more object oriented processors are embodied as a collection of components on a single ASIC chip. This related application includes an enhanced communication language where messages from one processor to another include source and destination addresses. This communication protocol can be said to be "event driven".
Co-owned prior application Ser. No. 09/004,174, now U.S. Pat. No. 6,052,729, discloses an object oriented processor array including a library of functional objects which are instantiated by commands through a system object and which communicate via a high level language. Communication is based on an "event-reaction" model. According to the event-reaction model, when a processor object has a message to send, it generates a data event which is registered with the target recipient of the message (usually the host). The target reacts to the event by allowing a variable amount of I/O exchange between the processor object and the target prior to an acknowledgement of the data event. According to one embodiment, until the data event is acknowledged, no other data event may be sent to the target. According to another embodiment, a fixed number of data events may be pending simultaneously. In one embodiment of a multi-node system, each node (each object oriented processor array) is aware of network traffic; and data events related to a particular target (host) receiver are registered with all nodes which have that receiver as a target as well as with the target. The number of data events which may be simultaneously pending at any time is determined by the target and known to each of the nodes. The target arbitrates the flow of messages based on the registration of data events.